1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure of a high breakdown voltage element for use in high power applications such as power devices.
2. Description of the Background Art
Power devices are widely used in home electric appliances and on-vehicle applications for driving and controlling of high power. The power devices include high-output power transistors which perform switching operations. The power transistors include power MOSFETs (insulated gate field effect transistors) and power bipolar transistors, and further IGBTs (insulated gate bipolar transistors) that are MOSFETs utilizing conductivity modulation. The IGBT has the characteristics that the input impedance is as high as the MOSFET and that the on-resistance can be reduced as in the bipolar transistor.
Device structures of the IGBT include a vertical structure and a lateral structure. In the IGBT having a vertical structure, an emitter electrode and a gate electrode are arranged opposing a collector electrode with respect to a substrate region of the device. In the IGBT having a lateral structure, an emitter electrode, a collector electrode and a gate electrode are placed on the same surface side of the device. Therefore, integration with other circuits such as a drive circuit is easy, and in recent years, IGBT having a lateral structure has been widely used in home electric appliances and on-vehicle applications.
Examples of the structure of the lateral IGBT are shown in Reference 1 (Japanese Patent Laying-Open No. 04-212464), Reference 2 (Japanese Patent Laying-Open No. 11-068106) and Reference 3 (Japanese Patent Laying-Open No. 02-185067).
In the configuration shown in Reference 1, an n-drift layer is formed in contact with the surface of a p− type substrate surface. The n− drift layer is an epitaxial layer. An n type buffer layer is formed on the surface of the n− drift layer. A p+ type collector region is formed, on the surface of the n type buffer layer, being surrounded by the buffer layer. In addition, on the surface of the n− drift layer, a p type base region is formed at a distance from the buffer layer. An n+ type emitter region is formed on the surface of the p type base region. The p type base region is coupled to the p− substrate by a high-impurity-concentration p+ type buried layer. The p+ type buried layer is formed to a depth deeper than the drift layer and extending into the p− substrate. The emitter electrode is provided so as to short-circuit the base region and the emitter region.
In the lateral IGBT shown in Reference 1, a first pnp bipolar transistor is formed by the p+ type collector region, the n buffer layer, the n− drift layer, the p− type substrate and the p+ type buried layer. In addition, a second pnp bipolar transistor is formed by the collector region, the n type buffer layer, the n− drift layer and the p type base region. The first and second pnp bipolar transistors are coupled in parallel.
In Reference 1, in the lateral IGBT structure, a rear side emitter electrode is formed on the rear surface of the p− substrate for the purpose of reducing a switching loss and preventing a latch-up phenomenon. The rear-side emitter electrode is short-circuited with an electrode formed on the emitter region. Due to the short circuit of the rear-side emitter electrode, a narrow base bipolar transistor is formed by the collector region, the buffer region, the n− drift layer and the p− substrate region. The on-voltage is lowered and the turn-off time is shortened taking advantage of a high current amplification factor of the narrow base bipolar transistor. In addition, the short circuit between the rear-side emitter electrode and the electrode on the emitter region, parallel operations of the first and second bipolar transistors are prevented. In this way, a hole current is divided into a lateral current and a vertical current, and the hole current is prevented from concentrating on the emitter region to inhibit the latch-up.
In the lateral IGBT shown in Reference 2 (Japanese Patent Laying-Open No. 11-068106), the p− substrate is connected to the back-surface electrode through a p+ diffusion layer doped at a high concentration. In Reference 2, by coupling the p− type substrate to the back surface electrode through the p+ diffusion layer, the lifetime of a charge carrier flowing through the p− type substrate is increased to increase the current load capability. Further, in Reference 2, as in Reference 1, the lateral current component is reduced to prevent the turn-on of a lateral parasitic thyristor to increase the latch-up immunity.
In addition, in Reference 2, the impurity concentration gradient of a p−/p+ junction region between the p− type substrate and the high-impurity-concentration p+ diffusion layer is decreased and the field intensity is locally reduced. In this way, an avalanche phenomenon resulting from a vertical current by holes is prevented from occurring.
Reference 2 also discloses a RESURF (Reduced Surface Field) structure for ensuring a high breakdown voltage. Reference 2 shows that if the RESURF region (drift layer) is formed with a diffusion layer, its doping concentration is desirable to be about 1E12/cm^2 (^ represents a power). It is disclosed that under such condition, a positive voltage is applied to an anode terminal (collector terminal) to reversely bias a pn junction between the drift layer and the base region and a junction portion between the drift layer and the p− substrate, whereby a depletion layer spreads throughout the n− type drift layer. It is also disclosed for the function of the buffer layer that the impurity concentration of the buffer layer is made higher than that of the n− drift layer, whereby the depletion layer can spread from the RESURF region (n− drift layer) to the anode region (collector region) to prevent occurrence of punch-through.
In the IGBT shown in Reference 3 (Japanese Patent Laying-Open No. 02-185067), an insulating layer is provided on the surface of the p− type substrate (bottom of the drift layer) in the area under the p type anode region (collector region). No insulating layer is provided in the area under the base region, and the p type base region is coupled to the p type substrate though the n− drift layer.
In Reference 3, the holes injected from the anode region (collector region) upon turn on are conducted to the base region through the drift layer while preventing the shunting of holes to the substrate direction by the insulating film. In this way, a conductivity modulation effect is fully taken advantages of, the on-resistance is reduced to reduce the on-voltage.
Furthermore, since no insulating film is formed in the area under the base region, the holes are absorbed through the substrate region in the area under the base region. Thus, a situation in which the hole current transferred from the collector region entirely flows from the based region to the cathode region (emitter region) is prevented to prevent occurrence of latch-up.
Reference 4 (U.S. Pat. No. 4,292,642) discusses the relationship between the depth of the drift layer and the length of the drift layer, based on distributions of a horizontal field and a vertical field, for improving the breakdown voltage performance by the RESURF structure.
In Reference 4, a low-impurity-concentration drift region of a different conductivity type is formed in the area under a low-impurity-concentration (low-concentration hereinbelow) base region. At the outer periphery of the low-concentration base region and the substrate region, a high-impurity-concentration (high-concentration hereinbelow) isolation region is provided at a distance from the base region. Reference 4 shows that if the depletion layer is allowed to spread from the low-concentration base region and the high-concentration isolation region on the outer periphery thereof to a low-concentration drift region at the lower side to fully deplete the low-concentration drift region, the breakdown voltage of the element is determined by a horizontal pn junction between the low-concentration base region and the low-concentration drift layer. Particularly, Reference 4 shows that the breakdown voltage can be increased by lowering the impurity concentrations of the low-concentration base region and the low-concentration drift region. Specifically, Reference 4 shows that if the distance between the high-concentration isolation region at the surface and the high-concentration base region is increased and the thickness of the low-concentration base region and the impurity concentration are decreased, the maximum value of the field intensity at the PN junction at the inside becomes higher than the field intensity at the surface to cause an dielectric breakdown at the internal horizontal PN junction. Particularly, Reference 4 discloses that by making the filed intensity along the surface of the low-concentration base layer symmetric, the maximum field intensity at the surface can be decreased, and calculates the impurity concentration of each region for increasing the breakdown voltage by full depletion in the RESURF structure described above in accordance with a calculation expressions.
As described above, in the lateral IGBT, the RESURF structure is generally used for achieving a high breakdown voltage performance. When the IGBT having the RESURF structure is in an off state, a positive bias is applied to the collector electrode to set a PN junction between the n− type drift layer and the p− type substrate to a reverse bias state. Under this condition, the entire region of the n type drift layer is depleted. Ideally, as disclosed in Reference 4, the surface field of the n type drift layer is made constant.
In other words, the full depleting of the n− drift layer is based on the premise that the n− drift layer is entirely depleted while the pn junction just below the collector electrode does not enter an avalanche state. In addition, as described in FIG. 12 of Reference 4, when the n− drift layer is easy to be excessively depleted, the depletion layer spreads along the surface to arrive at the collector electrode before the depletion layer from the pn junction between the drift layer on the lower side and the substrate region spreads, so that the surface field at the collector electrode side increases to cause a reduction in breakdown voltage. Therefore, as described previously, there is an optimum value called a RESURF condition in the total amount of impurity per unit area of the drift layer. The RESURF condition is 1E12/cm^2.
On the other hand, the vertical field just below the collector electrode is roughly a rectangular field approximated by one-dimensional step junction. In this case, a breakdown voltage of a p+/n/n−/p− junction in the area under the collector electrode can be calculated in a manner as shown in Reference 4.
Conventionally, the thickness t of the p− substrate is set to about 400 μm. The thickness of the p− substrate, i.e. 400 μm, is sufficiently large as compared to spread of the depletion layer (about 100 μm) just below the collector electrode. In this way, the risk that the deleted layer arrives at the rear-side electrode (backside emitter electrode) formed on the back surface of the substrate to cause the punch-through, is avoided. Furthermore, the thickness, t, is set to such thickness, since production has generally been made based on the mechanical strength of a semiconductor device and the general thickness of a substrate of a general integrated circuit chip.
However, recent analyses by inventors have revealed that an optimum range exists for the thickness, t, of the p− type substrate layer for which only the vertical spread of the depletion layer has been considered, and if the thickness t lies within the optimum range, various problems occur in terms of electric characteristics.
Namely, when the lateral IGBT is in an on state, the conductivity modulation occurs between the emitter and the collector due to injection of minority carriers, and most of the current flows between the emitter electrode and the collector electrode. In this case, a part of the current flows from the collector region through the drift layer and the substrate region to the rear surface electrode. For the vertical bipolar transistor operation component flowing in the longitudinal direction, if the thickness, t, of the p-type substrate increases, an area injected with minority carriers is widened, and an area influenced by the conductivity modulation spreads in the direction of the thickness of the p− type substrate. In this case, however, due to the thickness, t, of the p− type substrate, the resistance of the substrate region increases and the vertical bipolar transistor operation component decreases. In this case, the on-current slightly decreases as the thickness, t, increases.
On the other hand, when the thickness t of the p− type substrate is excessively small, the current component flowing from the collector electrode to the rear surface electrode excessively increases. Therefore, the conductivity modulation by minority carriers from the collector electrode to the emitter electrode is hindered, and the on-current abruptly decreases.
Furthermore, in the process of turn-off of the lateral IGBT, the voltage of the gate electrode is set to 0 V, and an electronic current via a channel formed in the area under the gate electrode with the insulating film arranged in between disappears (the channel is no longer formed). Thereafter, a major part of current components becomes a hole current injected from the collector region. In this state, if the thickness, t, of the p− type substrate is large, as for the hole current, the current component flowing along the surface directly to the emitter electrode becomes dominant. In this case, the distance through which the hole current is long, the resistance value becomes high, the collector voltage increases due to a voltage drop, the turn-off time becomes long to increase the turn-off loss.
Further, the current flowing into the emitter electrode becomes dominant, and due to a voltage drop in the base region, the base to emitter is forwardly biased, and a latch-up phenomenon tends to occur due to transition from a parasitic bipolar transistor operation to a thyristor operation. Accordingly, a problem of decrease in maximum controllable current arises.
For the relationship between the breakdown voltage characteristics and the thickness of the substrate, a similar problem arises in a lateral diode. If the substrate is thick, a problem of an increased turn-off loss and a decreased on-current arises depending on the relationship between the depth of the depletion layer spreading just below the cathode region and the thickness of the substrate.
In Reference 1, the electrode formed on the rear surface of the substrate is short-circuited with the emitter electrode, whereby concentration of a current on the emitter electrode is avoided to inhibit occurrence of latch-up. However, although Reference 1 discloses an IGBT having the RESULF structure, it does not discuss the relationship between the thickness of the substrate region, and the turn-off loss and the breakdown voltage.
In Reference 2, a high-concentration diffusion region is formed through diffusion of impurities in a low-concentration p type epitaxial layer, and an impurity concentration gradient is provided in the substrate region. By this configuration, an avalanche breakdown is suppressed, and the carrier lifetime is lengthened to increase the current load capability. However, although Reference 2 discloses a RESURF condition, it does not discuss the relationship between the thickness of the substrate region, and the breakdown voltage and the turn-off loss.
In Reference 3, for inhibiting the latch-up, an insulating layer is provided in the area under the collector region, the longitudinal hole current may be inhibited from flowing in the neighborhood of the collector region, to aim improvement in efficiency of injection of minority carriers for enhancing the effect of the conductivity modulation. However, although Reference 3 discloses a horizontal distance between the p type anode region (collector region) and the p type base region and a length of a buried insulating film formed at the lower layer, it does not discuss the relationship between the thickness of the underlying substrate and the breakdown voltage or turn-off loss.
In the configuration shown in Reference 4, it is disclosed that the distance between the lateral high-concentration region (isolation region) and the base region is made longer than the length of the depletion layer spreading from the pn junction at the interface of the isolation region, and the thickness of the drift layer is discussed along with the impurity concentration of the layer. However, Reference 4 does not discuss the relationship between the thickness of the underlying p− type substrate region, and the turn-off loss and the breakdown voltage. Reference 4 merely describes that the maximum value of the vertical field intensity is made higher than the maximum value of the horizontal surface field.